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The
“Understanding Serial ATA” course provides students
with a comprehensive insight into the operation of the Serial
ATA interface. The class examines the evolution of ATA, summarises
the operation of the parallel ATA interface and then explores
in detail the operation of Serial ATA at all architectural levels.
Serial ATA II Extensions are also thoroughly discussed. The class
concludes with a study of new application areas in which Serial
ATA will be deployed. Protocol analyser traces are used as an
aid to understanding.
Course Outline (click for details)
-
Introduction
| Details |
| |
History
and evolution of ATA |
| Parallel
ATA limitations |
| Moving to
a serial interface |
| Serial ATA
goals and objectives |
| Serial ATA
benefits |
| Comparison
of storage interfaces |
| New markets
for ATA devices |
-
ATA
Standards and Architecture
| Details |
| |
ANSI
and industry associations |
| Parallel
ATA standards |
| Serial ATA
standards |
| SATA architectural
layering |
| Understanding
terms and definitions |
| Sources
of information |
-
ATA Technical Overview
| Details |
| |
Parallel
bus functions |
| The I/O register model |
| CHS and LBA addressing |
| PIO and DMA data transfer modes |
-
Serial
ATA Technical Overview
| Details |
| |
SATA
architectural model |
| Physical layer concepts |
| Topology/connectivity |
| Power and signal lines |
|
Link speeds/data rates |
|
Basic SATA port model |
| Physical
layer services |
| Link layer
concepts |
| Transmission
words |
| 8b/10b encoding
concepts |
| Primitives |
| Framing
concepts |
| Scrambling |
| Transport
layer concepts |
| Frame Information
Structures (FIS) |
| FIS types |
| Error detection
and recovery concepts |
| Example
analyser trace |
| SATA II
enhancement summary |
-
Physical
Layer
| Details |
| |
Cables
and connectors |
| Electrical
signalling |
| Spread spectrum
clocking |
| Interface power states |
| Link initialisation |
| Speed negotiation |
| Out of band signalling |
| Elasticity buffering |
-
Link
Layer
| Details |
| |
Link layer services |
| 8b/10b encoding |
| Primitive signal definitions |
| Primitive signal protocols |
| Flow
control |
| Primitive
scrambling |
| CRC and
FIS content scrambling |
| Link
state diagrams |
| Example
analyser trace |
-
Transport
Layer
| Details |
| |
Transport
layer services |
|
FIS construction and decomposition |
|
FIS structure |
| FIS
types |
| Host
transport states |
| Device
transport states |
| Example
analyser trace |
-
Device
Command Layer Protocol
| Details |
| |
Power
on behaviour |
|
Device resets |
|
Diagnostics |
| Non-data command protocol |
| PIO command protocol |
| DMA command protocol |
-
Error
Handling
| Details |
| |
Physical
layer errors |
|
Link Layer errors |
|
Transport layer errors |
-
Serial
ATA II Extensions
| Details |
| |
SATA
II objectives |
|
Physical layer extensions |
|
Transport layer extensions |
| Command
layer extensions |
| Enclosure
services and management |
- Serial
ATA in the Enterprise
- Future
enhancements to Serial ATA
Who
Should Attend
This in-depth technical class is targeted towards engineers
involved in the design, development, integration, deployment
and maintenance of Serial ATA storage devices and systems.
Day 1 of the class may be taken by those requiring a broad
understanding of Serial ATA technology with less technical
depth; this includes technical managers, IT managers and staff,
technical writers, technical sales and marketing staff. |
| Prerequisites:
Some familiarity with computing and storage concepts. |
|
Course Length: 2 days |
Download course description (printable
version) |
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